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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:09:58 09/18/2013 
-- Design Name: 
-- Module Name:    adder_lookahead - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder_lookahead is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
			  C_in : STD_LOGIC;
           S : out  STD_LOGIC_VECTOR (3 downto 0);
           C : inout  STD_LOGIC_VECTOR (3 downto 0));
end adder_lookahead;

architecture Behavioral of adder_lookahead is
signal P : STD_LOGIC_VECTOR (3 downto 0);
signal G : STD_LOGIC_VECTOR (3 downto 0);
begin

P(0) <= A(0) or B(0);
P(1) <= A(1) or B(1);
P(2) <= A(2) or B(2);
P(3) <= A(3) or B(3);

G(0) <= A(0) and B(0);
G(1) <= A(1) and B(1);
G(2) <= A(2) and B(2);
G(3) <= A(3) and B(3);

C(0) <= G(0) or (P(0) and C_in);
C(1) <= G(1) or (P(1) and C(0));
C(2) <= G(2) or (P(2) and C(1));
C(3) <= G(3) or (P(3) and C(2));

S(0) <= (not A(0) and not B(0) and C_in) or (not A(0) and B(0) and not C_in) or (A(0) and not B(0) and not C_in) or (A(0) and B(0) and C_in);
S(1) <= (not A(1) and not B(1) and C(0)) or (not A(1) and B(1) and not C(0)) or (A(1) and not B(1) and not C(0)) or (A(1) and B(1) and C(0));
S(2) <= (not A(2) and not B(2) and C(1)) or (not A(2) and B(2) and not C(1)) or (A(2) and not B(2) and not C(1)) or (A(2) and B(2) and C(1));
S(3) <= (not A(3) and not B(3) and C(2)) or (not A(3) and B(3) and not C(2)) or (A(3) and not B(3) and not C(2)) or (A(3) and B(3) and C(2));

end Behavioral;

